Îmbunătățiri ale metricilor de performanță în verificarea funcțională a circuitelor utilizând Machine Learning / Performance metric improvements in circuit functional verification using Machine Learning

In this doctoral thesis, I research novel approaches to reduce the time costs for closing the functional verification tasks in integrated circuit development. Chapter 2 outlines a literature review, with a high emphasis on state-of-the-art synergies for reducing resource and time costs in functional verification. Specifically, I compare different AI-assisted engines that optimize key verification processes. Chapter 3 presents the theoretical fundamentals of the prime machine learning (ML) approaches identified in Chapter 2. The smart optimization principle for reducing the coverage closure time using stimuli redundancy reduction (SRR) is introduced. I also describe the principles of my novel supervised learning for stimuli redundancy reduction methodology(SL4SRRM) that I designed and proposed as the main implementation goal of this research. Chapter 4 introduces the implementation details of an original Coverage-Aware Stimuli Generation (CAStiG) framework that uses the novel SL4SRRM methodology. I describe the chosen technologies, other implementation approaches, the strongpoints of the framework, and the structure of the artificial neural network (ANN) that powers the tool. Chapter 5 presents the experimental results after deploying a series of use cases on the CAStiG framework. Different nonlinear coverage models are analyzed, and the CAStiG framework is compared with today’s standard, the coverage-driven verification (CDV) approach. Results indicate a reduction in the number of stimuli of up to 15000 in some cases. Finally, Chapter 6 draws the conclusions and highlights the original research contributions presented in this thesis. Moreover, future perspectives and further research directions are underlined in the final few lines