Low-power CMOS Design: Imagers and More

Bio

Since 2009 I am Associate Professor of the Electronics and Computer Science Department of the University of Santiago de Compostela (USC). Before, I had a postdoctoral position at the Fraunhofer Institute for Integrated Circuits in Erlangen, Germany (2003-04) and later an Isidro Parga Pondal Fellowship at the USC. Since April 2020 I am the deputy director of the Centro Singular de Investigación en Tecnoloxías Intelixentes (CiTIUS). Since 1999 I have authored or coauthored more than 90 scientific papers in peer-reviewed areas of modeling and characterization of semiconductor devices, microelectronics design, CMOS image sensors and image processing. I have participated in 18 I+D+I activities, in 8 of them as a Main Researcher, corresponding to I+D+I projects funded by competitive European (H2020) and national programs. I am the Scientific Coordinator and the main researcher of the USC team in the H2020 ETN MENELAOSNT and participate on the H2020 FETPROACT project MISEL. Over the years, I have participated in many actions to promote female STEM vocations. I have been involved in the organization of several national and international conferences. I am Secretary-Elect of the Sensory Systems Technical Committee (SSTC) of IEEE Circuits and Systems Society (CAS).

Abstract

The continuous scaling trend in CMOS technologies opens a whole new world of possibilities in the field of CMOS imagers design as it enables the embedding of different functionalities close to, and event at, the sensing element itself. This constitutes a new paradigm with respect to classic approaches in which image acquisition and processing were two separate stages of the whole signal processing path. Focal-plane and in-memory computing approaches are two of the enabling technologies that permit us to design cameras that generate information instead of simply data and open the door to develop hardware accelerators for deep neural networks. For this to become true, special attention has to be paid to the area/power factor. Strategies for drastically reducing the overall power consumption at circuit level need to be implemented. In this talk, examples of CMOS imagers with embedded sensing and processing capabilities will be presented as well as ultra-low power design strategies.