Optimizări algoritmice și arhitecturale pentru un accelerator hardware de tip Map-Reduce / Algorithmical and architectural improvements for a Map-Reduce hardware accelerator

In the context of modern parallel computing, systems are transitioning from tens and hundreds to thousands of computing cores on the same chip. Unfortunately, there is a major discrepancy between the theoretical maximum performance obtained in such computing systems. This situation motivates research into new architectures that can offer both higher performance and lower power consumption. This thesis aims at improving a massively parallel single chip Map-Reduce architecture. These improvements are regarding four main aspects: (1) adding new hardware blocks that offer new functionalities; (2) optimization and improvement of already present functionality; (3) improving parametrization and reconfigurability; (4) development of new end efficient algorithms that emphasize this computing architecture’s capabilities. The most important improvements are: (1) modifying the Beneš permutation network such that it supports permutation, scan, pack, reduce operations; (2) development of a hybrid accumulator and stack processor that can be used in both modes of operation; (3) adding support for floating point operations; (4) applications developed for computing the transpose of a square matrix and the Fast Fourier Transform. FPGA synthesis results are also given for the accelerator, with various features present. The proposed accelerator was integrated into an heterogenous computing system and tested on a Zynq 7020 SoC board